1. Field of the Invention
The present invention relates to a highly efficient DC (direct current) converter.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a DC converter according to a related art. The DC converter shown in FIG. 1 is a forward converter provided with active clamps. The DC converter includes a DC power source Vin and a main switch Q1 such as a MOSFET (field effect transistor) connected to the DC power source Vin through a primary winding P1 (having the number of turns of n1) of a transformer Ta.
Ends of the primary winding P1 are connected to a series circuit that consists of an auxiliary switch Q2 such as a MOSFET and a clamp capacitor C2. The series circuit consisting of the switch Q2 and clamp capacitor C2 forms an active clamp circuit, which may be connected in parallel with the switch Q1.
A diode D1 is connected between the drain and source of the switch Q1, and a diode D2 is connected between the drain and source of the switch Q2. The diodes D1 and D2 may be parasitic diodes of the switches Q1 and Q2 if the switches Q1 and Q2 are MOSFETs containing the parasitic diodes. A capacitor C3 is a voltage resonance capacitor and is connected between the drain and source of the switch Q1. The capacitor C3 may be a parasitic capacitance of the switch Q1.
The switches Q1 and Q2 have a dead time during which they are both turned off by a control circuit 11. The control circuit 11 conducts PWM control to alternately turn on/off the switches Q1 and Q2.
The primary winding P1 and a secondary winding S1 (having the number of turns of n2) of the transformer Ta are wound to generate in-phase voltages. In FIG. 1, a filled circle represents a winding start of each of the primary winding P1 and secondary winding S1 of the transformer Ta.
A leakage inductance LS is produced between the primary winding P1 and the secondary winding S1 of the transformer Ta. Through the leakage inductance LS, a first end of the secondary winding S1 is connected to the cathode of a diode D10. A second end (indicated with the filled circle) of the secondary winding S1 is connected to the cathode of a diode D11. The anode of the diode D11 is connected to the anode of the diode D10.
The ends of the diode D10 are connected to the drain and source of a switch Q10, which may be a MOSFET serving as a synchronous rectifier for rectification. The ends of the diode D11 are connected to the drain and source of a switch Q11, which may be a MOSFET serving as a synchronous rectifier for current circulation. The gate of the switch Q10 is connected to the second end (indicated with the filled circle) of the secondary winding S1. The gate of the switch Q11 is connected through the leakage inductance LS to the first end of the secondary winding S1.
The diodes D10 and D11 may be parasitic diodes of the switches Q10 and Q11 if the switches Q10 and Q11 are MOSFETs containing the parasitic diodes. The elements D10, D11, Q10, and Q11 form a synchronous rectifying circuit. The synchronous rectifying circuit rectifies voltage (on/off-controlled pulse voltage), which is generated by the secondary winding S1 of the transformer Ta in synchronization with on/off operation of the switch Q1, and outputs the rectified voltage.
The ends of the diode D10 are connected to a series circuit including a resistor R20 and a capacitor C20. The ends of the diodes D11 are connected to a series circuit including a resistor R21 and a capacitor C21. These two series circuits are CR snubber circuits to attenuate surge voltage during recovery of the diodes D10 and D11.
The ends of the switch Q11 are connected in series with a smoothing reactor L1 (corresponding to a smoothing element) and a smoothing capacitor C10 (corresponding to a smoothing element), to form a smoothing circuit. The smoothing circuit smoothes the rectified output of the synchronous rectifying circuit and provides a DC output to a load 50.
Based on an output voltage of the load 50, the control circuit 11 generates a pulse control signal to turn on/off the switches Q1 and Q2, and at the same time, controls the duty factor of the control signal so as to bring the output voltage to a predetermined value.
The DC converter also includes a low-side driver 13 and a high-side driver 15. The low-side driver 13 applies a gate signal Q1g from the control circuit 11 to the gate of the switch Q1, to thereby drive the switch Q1. The high-side driver 15 applies a gate signal Q2g from the control circuit 11 to the gate of the switch Q2, to thereby drive the switch Q2.
Operation of the DC converter of the above-mentioned configuration will be explained with reference to a timing chart of FIG. 2. In FIG. 2, Q1g is a gate signal to the switch Q1, Q2g a gate signal to the switch Q2, Q1v a drain-source voltage of the switch Q1, Q1i a drain current of the switch Q1, Q2i a drain current of the switch Q2, C3i a current to the capacitor C3, Q10v a drain-source voltage of the switch Q10, D10i a current to the diode D10, Q10i a drain current of the switch Q10, Q11v a drain-source voltage of the switch Q11, D11i a current to the diode D11, and Q11i a drain current of the switch Q11.
Before t0, the switch Q1 is OFF and the switch Q2 ON. On the primary side of the transformer Ta, a current passes through a path along Q2, P1, C2, and Q2. The primary winding P1 of the transformer Ta receives a voltage VC2 from the clamp capacitor C2, and the potential of the winding end of the primary winding P1 is positive. Accordingly, a terminal voltage of the secondary winding S1 is expressed by VC2·(n2/n1) and the potential of the winding end of the secondary winding S1 is positive.
As a result, the voltage Q10v of the switch Q10 is equal to VC2·(n2/n1) and the gate voltage of the switch Q11 is expressed by VC2·(n2/n1) and is positive. This turns on the switch Q11. On the secondary side of the transformer Ta, a current passes through a route of L1, C10, Q11, and L1. The voltage Q11v is substantially zero and the switch Q10 is OFF.
At t0 of period T1, the switch Q2 changes from ON to OFF and the current passing through the path along Q2, P1, C2, and Q2 becomes zero. Instead, a current passes through a path along P1, Vin, C3, and P1, to discharge the capacitor C3 and drop the voltage Q1v of the switch Q1. When the voltage Q1v drops, the terminal voltage of the primary winding P1 decreases to decrease the terminal voltage of the secondary winding S1. This results in decreasing the voltage Q10v of the switch Q10.
At t1 of period T2, the voltage Q10v of the switch Q10 decreases to a gate threshold voltage Vth11 of the switch Q11, to turn off the switch Q11. The current Q11i of the switch Q11 becomes zero, and the current to the switch Q11 starts to pass through the diode D11.
At t2 of period T3, the voltage Q1v of the switch Q1 reaches the voltage of the DC power source Vin. The terminal voltage of the primary winding P1 becomes zero, and therefore, the terminal voltage of the secondary winding S1 becomes zero. This drops the voltage Q10v of the switch Q10 to zero. The voltage Q1v of the switch Q1 further decreases to apply positive potential to the winding start of the primary winding P1, and therefore, positive potential is applied to the winding start of the secondary winding S1. At t3, the voltage Q1v of the switch Q1 becomes zero. Then, the terminal voltage of the primary winding P1 becomes Vin and the terminal voltage of the secondary winding S1 becomes Vin·(n2/n1). In the period T3, the terminal voltage of the primary winding P1 changes from zero to Vin with the winding start of the primary winding P1 being positive. At this time, the terminal voltage of the secondary winding S1 changes from zero to Vin·(n2/n1) with the winding start of the secondary winding S1 being positive.
Accordingly, a current ILS(t) passing through the leakage inductance LS increases according to following expression:ILS(t)=(VS1(t)/LS)·t   (1),where VS1(t) is a terminal voltage of the secondary winding S1, LS is a leakage inductance value, and t is time. The current passing through the leakage inductance LS is equal to the current of the diode D10, and therefore, the current D10i of the diode D10 increases in the period T3. By an increment of the current D10i of the diode D10, the current D11i of the diode D11 decreases. During the period T3 on the secondary side of the transformer Ta, a current passes through a route of L1, C10, D11, and L1 and another current passes through a route of L1, C10, D10, LS, S1, and L1. The latter current increases according to the expression (1), and the former current decreases thereby.
At t3 of period T4, the capacitor C3 completely discharges, the voltage Q1v of the switch Q1 becomes zero, the current passing through the path along P1, Vin, C3, and P1 changes its direction to a path along P1, Vin, D1 (Q1), and P1, and the switch Q1 turns on in response to the gate signal Q1g. 
In the period T4, the voltage Q1v of the switch Q1 is substantially zero and the terminal voltage of the primary winding P1 is Vin. The terminal voltage VS1(t) of the secondary winding S1, therefore, is expressed as Vin·(n2/n1). The current ILS(t) passing through the leakage inductance LS increases according to following expression:
                                                                                                                                    ILS                      ⁡                                              (                        t                        )                                                              =                                                                  (                                                  VS                          ⁢                                                                                                          ⁢                          1                          ⁢                                                      (                            t                            )                                                                          )                                            /                      LS                                                        )                                ·                t                            +                              ILS                ⁡                                  (                                      t                    ⁢                                                                                  ⁢                    3                                    )                                                                                                                        =                                                                            (                                              Vin                        ·                                                                              (                                                          n                              ⁢                                                                                                                          ⁢                                                              2                                /                                n                                                            ⁢                                                                                                                          ⁢                              1                                                        )                                                    /                          LS                                                                    )                                        ·                    t                                    +                                      ILS                    ⁡                                          (                                              t                        ⁢                                                                                                  ⁢                        3                                            )                                                                                  ,                                                          (        2        )            where ILS(t3) is a current passing through the leakage inductance LS at t3. By an increment of the current passing through the leakage inductance LS, the current D11i of the diode D11 decreases and reaches at t4 a current passing through the smoothing reactor L1. Then, the current ILS(t) becomes equal to the current of the smoothing reactor L1, the current D11i of the diode D11 becomes zero, and the diode D11 passes a reverse current due to a recovery current of the diode D11. The current Q1i of the switch Q1 is proportional to a current passing through the secondary winding S1 at the ratio of the numbers of turns. The current Q1i of the switch Q1, therefore, increases and reaches at t4 a value of n2/n1 (the ratio of the numbers of turns) times a current passing through the smoothing reactor L1.
At t4 of period T5, the recovery current of the diode D11 decreases, and the voltage Q11v of the switch Q11 increases. When the voltage Q11v of the switch Q11 reaches a gate threshold voltage Vth10 of the switch Q10, the switch Q10 turns on so that a current passing through the diode D10 changes its direction to the switch Q10. The voltage Q11v of the switch Q11 oscillates due to the joint capacitance of the leakage inductance LS and diode D11 and the output capacitance of the switch Q11. The oscillation gradually attenuates, and the voltage Q11v of the switch Q11 settles to be Vin·(n2/n1).
If the voltage Q11v of the switch Q11 oscillates to cross the gate threshold voltage Vth10 of the switch Q10, the switch Q10 repeatedly turns on and off to cause chattering as shown in an operational waveform of FIG. 6 involving large ringing. To suppress such oscillation, the CR snubber circuit consisting of the resistor R21 and capacitor C21 may be added. Since the primary winding P1 and secondary winding S1 are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.
At t5 of period T6, the gate signal Q1g of the switch Q1 falls to zero, thereby zeroing the current Q1i of the switch Q1. The current passing through the route of Vin, P1, Q1, and Vin starts to change to a route of Vin, P1, C3, and Vin, to increase the voltage of the capacitor C3. As a result, the voltage Q1v of the switch Q1 increases and the voltage Q11v of the switch Q11 decreases.
At t6 of period T7, the voltage Q11v of the switch Q11 decreases to the gate threshold voltage Vth10 of the switch Q10. The switch Q10 turns off to zero the current Q10i of the switch Q10, and the current passing through the switch Q10 changes its direction to the diode D10.
At t7 of period T8, the voltage Q1v of the switch Q1 reaches Vin. The terminal voltage of the primary winding P1 becomes zero and the terminal voltage of the secondary winding S1 also becomes zero to zero the voltage Q11v of the switch Q11. The voltage Q1v of the switch Q1 further increases to apply positive potential to the winding end of the primary winding P1. The winding end of the secondary winding S1 also receives positive potential. At t8, the voltage Q1v of the switch Q1 reaches level of Vin+VC2. As a result, the terminal voltage of the primary winding P1 becomes VC2 and that of the secondary winding S1 becomes VC2·(n2/n1). In the period T8, the terminal voltage of the primary winding P1 with its winding end receiving positive potential changes from zero to VC2. At this time, the terminal potential of the secondary winding S1 with its winding end receiving positive potential changes from zero to a level of VC2·(n2/n1). Accordingly, the current ILS(t) passing through the leakage inductance LS decreases according to following expression:ILS(t)=ILS(t7)−(VS1(t)/LS)·t   (3),where VS1(t) is the terminal voltage of the secondary winding S1 and ILS(t7) is a current passing through the leakage inductance LS at t7. The current passing through the leakage inductance LS is equal to the current passing through the diode D10, and therefore, the current D10i of the diode D10 decreases in the period T8. By a decrement in the current D10i of the diode D10, the current D11i of the diode D11 increases.
In the period T8 on the secondary side of the transformer Ta, a current passes through the route of L1, C10, D10, LS, S1, and L1 and another current passes through the route of L1, C10, D11, and L1. The former current decreases according to the expression (3), and the latter current increases by the decrement of the former current.
At t8 of period T9, the capacitor C3 is completely charged, the voltage Q1v of the switch Q1 is substantially a level of Vin+VC2, and the terminal voltage of the primary winding P1 is VC2. Accordingly, the terminal voltage VS1(t) of the secondary winding S1 is a level of VC2·(n2/n1) and the current ILS(t) passing through the leakage inductance LS decreases according to following expression:
                                                                        ILS                ⁡                                  (                  t                  )                                            =                                                ILS                  ⁢                                                                          ⁢                                      (                                          t                      ⁢                                                                                          ⁢                      8                                        )                                                  -                                                      (                                          VS                      ⁢                                                                                          ⁢                      1                      ⁢                                                                        (                          t                          )                                                /                        LS                                                              )                                    ·                  t                                                                                                                        =                                                      ILS                    ⁢                                                                                  ⁢                                          (                                              t                        ⁢                                                                                                  ⁢                        8                                            )                                                        -                                                            (                                              VC                        ⁢                                                                                                  ⁢                                                  2                          ·                                                                                    (                                                              n                                ⁢                                                                                                                                  ⁢                                                                  2                                  /                                  n                                                                ⁢                                                                                                                                  ⁢                                1                                                            )                                                        /                            LS                                                                                              )                                        ·                    t                                                              ,                                                          (        4        )            where ILS(t8) is a current passing through the leakage inductance LS at t8. In this way, the current passing through the leakage inductance LS decreases, and by this decrement, the current D11i of the diode D11 increases. At t9, the current D10i of the diode D10 becomes zero, and the diode D10 passes a reverse current due to a recovery current. The current D11i of the diode D11 becomes equal to a current passing through the smoothing reactor L1. The current Q2i of the switch Q2 is proportional to a current passing through the secondary winding S1 at the ratio of the numbers of turns. Namely, the current Q2i of the switch Q2 increases and becomes an excitation current of the primary winding P1 at t9.
At t9 of period T10, the recovery current of the diode D10 decreases and the voltage Q10v of the switch Q10 increases. The voltage Q10v reaches the gate threshold voltage Vth11 of the switch Q11 to turn on the switch Q11. Then, a current passing to the diode D11 changes its direction to the switch Q11.
The voltage Q10v of the switch Q10 oscillates due to the joint capacitance of the leakage inductance LS and diode D10 and the output capacitance of the switch Q10. The oscillation of the voltage Q10v gradually attenuates and reaches a level of VC2·(n2/n1).
If the voltage Q10v of the switch Q10 oscillates to cross the gate threshold voltage Vth11 of the switch Q11, the switch Q11 repeatedly turns on and off to cause chattering as shown in an operational waveform of FIG. 6 involving large ringing. To suppress such oscillation, the CR snubber circuit consisting of the resistor R20 and capacitor C20 may be added. Since the primary winding P1 and secondary winding S1 are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.
In this way, driving the synchronous rectifiers by the secondary winding S1 according to the related art passes a current to the diode D10 in the periods T3, T4, T7, T8, and T9 and a current to the diode D11 in the periods T2, T3, T4, T8, and T9. Namely, during these periods, no current passes through the synchronous rectifiers (switches Q10 and Q11). Instead, the currents pass through the diodes D10 and D11 during the periods, thereby deteriorating the efficiency of synchronous rectification and the efficiency of a power source. In addition, the diodes D10 and D11 connected in parallel with the synchronous rectifiers produce recovery currents that repeatedly turn on/off the synchronous rectifiers. This results in causing the chattering of the synchronous rectifiers and deteriorating efficiency. Adding the CR snubber circuits to suppress the chattering will increase losses and deteriorate efficiency.
FIG. 3 is a circuit diagram showing a DC converter according to a second related art. In FIG. 3, the primary side of a transformer Tb employs an active clamp circuit and is the same as the primary side of the transformer Ta of FIG. 1, and therefore, the explanation thereof is omitted. The transformer Tb has a primary winding (having the number of turns of n1), a first secondary winding S1 (having the number of turns of n2) very loosely coupled with the primary winding P1, and a second secondary winding S2 (having the number of turns of n3) loosely coupled with the primary winding P1. A first end of the first secondary winding S1 is connected to a first end of the second secondary winding S2. The ends of the first secondary winding S1 are connected through a leakage inductance L1 to a saturable reactor LH. The saturable reactor LH is formed with the use of the saturation characteristic of a core of the transformer Tb.
A second end (indicated with a filled circle) of the second secondary winding S2 is connected through a leakage inductance LS to the cathode of a diode D11. The first end of the second secondary winding S2 is connected to the cathode of a diode D10. The anode of the diode D10 is connected to the anode of the diode D11.
The ends of the diode D10 are connected to the drain and source of a switch Q10 such as a MOSFET. The ends of the diode D11 are connected to the drain and source of a switch Q11 such as a MOSFET. The gate of the switch Q11 is connected to the first end of the second secondary winding S2. The gate of the switch Q10 is connected through the leakage inductance LS to the second end of the second secondary winding S2. The second end of the first secondary winding S1 is connected through the leakage inductance L1 to a first end of a capacitor C10. A second end of the capacitor C10 is connected to a node between the anode of the diode D10 and the anode of the diode D11.
The leakage inductance LS exists between the loosely coupled primary winding P1 and second secondary winding S2. The leakage inductance L1 between the very loosely coupled primary winding P1 and first secondary winding S1 serves as a smoothing reactor of the forward converter and accumulates energy when a switch Q1 is ON. When the switch Q1 is OFF, the second secondary winding S2 returns the energy accumulated in the leakage inductance L1 to the secondary side of the transformer Tb.
The leakage inductance LS stores energy accumulated when the switch Q1 is ON into a clamp capacitor C2, to drop a core around which the first secondary winding S1 is wound to the third quadrant and saturate the same.
FIG. 4 is a view showing the structure of the transformer Tb of the DC converter according to the second related art. FIG. 5 is an equivalent circuit diagram showing the transformer of FIG. 4. In FIG. 4, the transformer Tb has a core 30 having a rectangular external shape. The core 30 has spaces 35a and 35b extending in parallel to each other in a longitudinal magnetic path direction, to form magnetic paths 32a, 32b, and 32c. Around a core part 30a of the core 30, the primary winding P1 and second secondary winding S2 are wound adjacent to each other. This produces the slight leakage inductance LS between the primary winding P1 and the second secondary winding S2. The core 30 has a path core 30c and a gap 31. Around a peripheral core, the first secondary winding S1 is wound. The path core 30c works to very loosely couple the primary winding P1 and first secondary winding S1 with each other, thereby increasing the leakage inductance L1.
On the peripheral core and between the primary winding P1 and the second secondary winding S2, a recess 30b is formed. The recess 30b reduces the sectional area of a part of a magnetic path of the core so that only the part may saturate. This configuration can reduce a core loss. The part that saturates is used as the saturable reactor LH. Forming the recess 30b at a part of the core 30 where the first secondary winding S1 is wound results in saturating the part, increasing an excitation current, and producing a voltage resonance. Black dots shown in FIG. 5 indicate the winding starts of the primary winding P1, first secondary winding S1, and second secondary winding S2 of the transformer Tb.
Operation of the DC converter of FIG. 3 will be explained with reference to a timing chart of FIG. 7.
Before t0, the switch Q1 is OFF and the switch Q2 ON. On the primary side of the transformer Tb, a current passes through a route of Q2, P1, C2, and Q2. On the secondary side of the transformer Tb, a current passes through a route of L1, C10, Q11, LS, S2, S1, and L1. A voltage Q11v of the switch Q11 is substantially zero. The switch Q10 is OFF. The primary winding P1 of the transformer Tb receives a voltage VC2 from the clamp capacitor C2, and the potential of the winding end of the primary winding P1 is positive. Accordingly, a terminal voltage of the second secondary winding S2 is a level of VC2·(n3/n1) and the potential of the winding end of the second secondary winding S2 is positive.
The voltage of the first secondary winding S1 (including the leakage inductance L1) is a level of VC2·(n3/n1)−Vout and the potential of the winding end of the first secondary winding S1 is positive. The voltage Q10v of the switch Q10, therefore, is positive and is equal to a level of VC2·(n3/n1). Namely, the gate voltage of the switch Q11 is positive, and therefore, the switch Q11 is ON.
At t0 of period T1, the switch Q2 changes from ON to OFF and a current passing through the path along Q2, P1, C2, and Q2 becomes zero. Instead, a current passes through a path along P1, Vin, C3, and P1, to discharge a capacitor C3 and drop the voltage Q1v of the switch Q1. When the voltage Q1v drops, the terminal voltage of the primary winding P1 decreases to decrease the terminal voltage of the second secondary winding S2. This results in decreasing the voltage Q10v of the switch Q10.
At t1 of period T2, the voltage Q10v of the switch Q10 decreases to a gate threshold voltage Vth11 of the switch Q11, to turn off the switch Q11. A current Q11i of the switch Q11 becomes zero, and the current to the switch Q11 starts to pass through the diode D11.
At t2 of period T3, the voltage Q1v of the switch Q1 reaches Vin. The terminal voltage of the primary winding P1 becomes zero, and therefore, the terminal voltage of the second secondary winding S2 becomes zero. This drops the voltage Q10v of the switch Q10 to zero. The voltage Q1v of the switch Q1 further decreases to apply positive potential to the winding start of the primary winding P1, and therefore, positive potential is applied to the winding start of the second secondary winding S2. At t3, the voltage Q1v of the switch Q1 becomes zero. Then, the terminal voltage of the primary winding P1 becomes Vin and the terminal voltage of the second secondary winding S2 becomes a value of Vin·(n3/n1). In the period T3, the terminal voltage of the primary winding P1 changes from zero to Vin with the winding start of the primary winding P1 being positive. At this time, the terminal voltage of the second secondary winding S2 changes from zero to a level of Vin·(n3/n1) with the winding start of the second secondary winding S2 being positive.
Accordingly, a current ILS(t) passing through the leakage inductance LS decreases according to following expression:ILS(t)=ILS(t2)−(VS2(t)/LS)·t   (5),where VS2(t) is a terminal voltage of the second secondary winding S2 and ILS(t2) is a current passing through the leakage inductance LS at t2. The current passing through the leakage inductance LS is equal to the current of the diode D11, and therefore, the current D11i of the diode D11 decreases in the period T3.
By a decrement of the current D11i of the diode D11, the current D10i of the diode D10 increases. During the period T3 on the secondary side of the transformer Tb, a current passes through a path along L1, C10, D11, LS, S2, S1, and L1 and another current passes through a path along L1, C10, D10, S1, and L1. The former current decreases according to the expression (5), and the latter current increases thereby.
At t3 of period T4, the capacitor C3 completely discharges, the voltage Q1v of the switch Q1 becomes zero, the current passing through the path along P1, Vin, C3, and P1 changes its direction to a path along P1, Vin, D1 (Q1), and P1, and the switch Q1 turns on in response to a gate signal Q1g. 
In the period T4, the voltage Q1v of the switch Q1 is substantially zero and the terminal voltage of the primary winding P1 is Vin. The terminal voltage VS2(t) of the second secondary winding S2, therefore, is a level of Vin·(n3/n1). The current ILS(t) passing through the leakage inductance LS decreases according to following expression:
                                                                        ILS                ⁡                                  (                  t                  )                                            =                                                ILS                  ⁢                                                                          ⁢                                      (                                          t                      ⁢                                                                                          ⁢                      3                                        )                                                  -                                                      (                                          VS                      ⁢                                                                                          ⁢                      2                      ⁢                                                                        (                          t                          )                                                /                        LS                                                              )                                    ·                  t                                                                                                                        =                                                      ILS                    ⁢                                                                                  ⁢                                          (                                              t                        ⁢                                                                                                  ⁢                        3                                            )                                                        -                                                            (                                              Vin                        ⁢                                                                                                  ·                                                                              (                                                          n                              ⁢                                                                                                                          ⁢                                                              3                                /                                n                                                            ⁢                                                                                                                          ⁢                              1                                                        )                                                    /                          LS                                                                    )                                        ·                    t                                                              ,                                                          (        6        )            where ILS(t3) is a current passing through the leakage inductance LS at t3. By a decrement of the current passing through the leakage inductance LS, the current D10i of the diode D10 increases. At t4, the current D10i of the diode D10 reaches a current passing through the leakage inductance L1. Then, the current D11i of the diode D11 becomes zero and the diode D11 passes a reverse current due to a recovery current of the diode D11.
The current Q1i of the switch Q1 is proportional to a current passing through the second secondary winding S2 at the ratio of the numbers of turns. The current Q1i of the switch Q1, therefore, increases and reaches at t4 the ratio of the numbers of turns times the current passing through the leakage inductance L1.
At t4 of period T5, the recovery current of the diode D11 decreases, and the voltage Q11v of the switch Q11 increases. When the voltage Q11v of the switch Q11 reaches a gate threshold voltage Vth10 of the switch Q10, the switch Q10 turns on so that the current passing through the diode D10 changes its direction to the switch Q10. The voltage Q11v of the switch Q11 oscillates due to the joint capacitance of the leakage inductance LS and diode D11 and the output capacitance of the switch Q11. The oscillation gradually attenuates, and the voltage Q11v of the switch Q11 settles to a level of Vin·(n3/n1).
If the voltage Q11v of the switch Q11 oscillates to cross the gate threshold voltage Vth10 of the switch Q10, the switch Q10 repeatedly turns on and off to cause chattering as shown in the operational waveform of FIG. 6 involving large ringing. To suppress such oscillation, a CR snubber circuit consisting of a resistor R21 and a capacitor C21 may be added. Since the primary winding P1 and second secondary winding S2 are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.
At t5 of period T6, the gate signal Q1g of the switch Q1 falls to zero, to zero the current Q1i of the switch Q1. The current passing through the path along Vin, P1, Q1, and Vin starts to change to the route of Vin, P1, C3, and Vin, to increase the voltage of the capacitor C3. As a result, the voltage Q1v of the switch Q1 increases and the voltage Q11v of the switch Q11 decreases.
At t6 of period T7, the voltage Q11v of the switch Q11 decreases to the gate threshold voltage Vth10 of the switch Q10. The switch Q10 turns off to zero the current Q10i of the switch Q10, and the current passing through the switch Q10 changes its direction to the diode D10.
At t7 of period T8, the voltage Q1v of the switch Q1 reaches Vin. The terminal voltage of the primary winding P1 becomes zero and the terminal voltage of the second secondary winding S2 also becomes zero to zero the voltage Q11v of the switch Q11. The voltage Q1v of the switch Q1 further increases to apply positive potential to the winding end of the primary winding P1. The winding end of the second secondary winding S2 also receives positive potential. At t8, the voltage Q1v of the switch Q1 reaches a level of Vin+VC2. As a result, the terminal voltage of the primary winding P1 becomes VC2 and that of the second secondary winding S2 becomes a level of VC2·(n3/n1).
In the period T8, the terminal voltage of the primary winding P1 with its winding end receiving positive potential changes from zero to VC2. At this time, the terminal potential of the second secondary winding S2 with its winding end receiving positive potential changes from zero to a level of VC2·(n3/n1). Accordingly, the current ILS(t) passing through the leakage inductance LS increases according to following expression:ILS(t)=(VS2(t)/LS)·t   (7),where VS2 (t) is the terminal voltage of the second secondary winding S2. The current passing through the leakage inductance LS is equal to the current passing through the diode D11, and therefore, the current D11i of the diode D11 increases in the period T8. By an increment in the current D11i of the diode D11, the current D10i of the diode D10 decreases.
In the period T8 on the secondary side of the transformer Tb, a current passes through the route of L1, C10, D10, S1, and L1 and another current passes through the route of L1, C10, D11, LS, S2, S1, and L1. The latter current increases according to the expression (7), and the former current decreases by the increment of the latter current.
At t8 of period T9, the capacitor C3 is completely charged, the voltage Q1v of the switch Q1 is substantially a level of Vin+VC2, and the terminal voltage of the primary winding P1 is VC2. Accordingly, the terminal voltage VS2(t) of the second secondary winding S2 is a level of VC2·(n3/n1) and the current ILS(t) passing through the leakage inductance LS increases according to following expression:
                                                                        ILS                ⁡                                  (                  t                  )                                            =                                                ILS                  ⁢                                                                          ⁢                                      (                                          t                      ⁢                                                                                          ⁢                      8                                        )                                                  -                                                      (                                          VS                      ⁢                                                                                          ⁢                      2                      ⁢                                                                        (                          t                          )                                                /                        LS                                                              )                                    ·                  t                                                                                                                        =                                                      ILS                    ⁢                                                                                  ⁢                                          (                                              t                        ⁢                                                                                                  ⁢                        8                                            )                                                        -                                                            (                                              VC                        ⁢                                                                                                  ⁢                                                  2                          ⁢                                                                                                          ·                                                                                    (                                                              n                                ⁢                                                                                                                                  ⁢                                                                  3                                  /                                  n                                                                ⁢                                                                                                                                  ⁢                                1                                                            )                                                        /                            LS                                                                                              )                                        ·                    t                                                              ,                                                          (        8        )            where ILS(t8) is a current passing through the leakage inductance LS at t8. In this way, the current passing through the leakage inductance LS increases, and by this increment, the current D10i of the diode D10 decreases. At t9, the current D10i of the diode D10 becomes zero, and the diode D10 passes a reverse current due to a recovery current. The current D11i of the diode D11 becomes equal to a current passing through the leakage inductance L1. The current Q2i of the switch Q2 is proportional to a current passing through the second secondary winding S2 at the ratio of the numbers of turns. Namely, the current Q2i of the switch Q2 increases and becomes an excitation current of the primary winding P1 at t9.
At t9 of period T10, the recovery current of the diode D10 decreases and the voltage Q10v of the switch Q10 increases. The voltage Q10v reaches the gate threshold voltage Vth11 of the switch Q11 to turn on the switch Q11. Then, a current passing through the diode D11 changes its direction to the switch Q11. The voltage Q10v of the switch Q10 oscillates due to the joint capacitance of the leakage inductance LS and diode D10 and the output capacitance of the switch Q10. The oscillation of the voltage Q10v gradually attenuates and reaches a level of VC2·(n3/n1).
If the voltage Q10v of the switch Q10 oscillates to cross the gate threshold voltage Vth11 of the switch Q11, the switch Q11 repeatedly turns on and off to cause chattering as shown in the operational waveform of FIG. 6 involving large ringing. To suppress such oscillation, a CR snubber circuit consisting of a resistor R20 and a capacitor C20 may be added. Since the primary winding P1 and second secondary winding S2 are loosely coupled to increase the leakage inductance LS, the amplitude of the oscillation is large and the frequency thereof is low. This results in increasing a loss of the CR snubber circuit and deteriorating efficacy.